The present invention relates generally to the measurement of critical dimensions in semiconductor processing. More particularly, it relates to the measurement of critical dimensions of etched features.
In the semiconductor industry, it is widely recognized that reducing the size of electrical elements (e.g. transistors, capacitors, interconnects and the like) in integrated circuits has the potential to provide a number of benefits in terms of device performance and functionality. Increased proximity of devices generally reduces signal propagation time and increases noise immunity while increased numbers of electrical elements on a chip of a given size generally allow increased circuit complexity and additional signal processing functions to be provided. Improved economy of manufacture also generally results from increased integration density since more electrical elements can be simultaneously formed by a given process. Therefore, there are ongoing efforts to develop technologies that facilitate the fabrication of integrated circuits having smaller and more densely packed electrical components. By way of example, some current state of the art technologies incorporate 0.18 μm (micron) line width design rules. The industry is currently developing devices implementing next generation design rules (e.g., 0.13 μm, 0.08 μm etc.) and it is fully expected that in the coming years these dimensions will be further reduced.
One important aspect of semiconductor processing is the precise control of the critical dimensions (e.g. width) of the various electrical elements that are formed within an integrated circuit. Therefore, over the years, extensive efforts have been made to facilitate the measurement of critical dimensions. It should be appreciated that there are a number of stages in the fabrication process where the measurement of critical dimensions becomes important. For example, the measurement of critical dimensions is perceived to be critical during the lithographic process. A lithographic process generally includes the exposure of a resist with some form of energy (e.g. light, charged particles, x-rays, etc.) to which the resist is sensitive in a pattern which is subsequently developed to remove selected areas of the resist to allow processes to be selectively carried out where resist has been removed. Generally, at least one lithographic process is required for the formation of any active or passive electrical element in order to define its location and its basic dimensions.
In state of the art semiconductor processing, some of the semiconductor structures being formed have dimensions smaller than lithographic resolution. Therefore, the quality of the exposure of the resist is of paramount importance to the formation of integrated circuits in accordance with a given design. Accordingly, there have been extensive efforts to develop techniques for accurately measuring critical dimensions in lithography processes. By way of example, in U.S. Pat. No. 6,094,256 (which is incorporated herein by reference), the present inventor (and others) proposed the optical measurement of the length of specially designed test marks to facilitate the calculation of critical dimensions in photoresists The measured mark is formed by the exposure of a particular feature (e.g. a line, bar, etc.) at each of two overlapping orientations that are rotated about an axis with respect to each other. In pending U.S. patent application Ser. No. 09/861,541, filed May 22, 2001 (which is also incorporated herein by reference), an improvement of this process which effectively measures the areas of the test marks is described.
Another area where the measurement of critical dimensions is very important relates to etch monitoring and characterization. A wide variety of etching processes are typically used during semiconductor fabrication. Since etching involves chemical reactions which may be influenced by a wide variety of factors, it can be difficult to precisely control etch processes and it is not uncommon for the characteristics of a particular etch process to vary over time. Therefore, extensive efforts are typically made to measure the critical dimensions of etched features. However, the current critical dimension measurement (or inference) techniques have a number of drawbacks. Some require the periodic insertion of special (and expensive) test wafers into the production stream. The test wafer are processed using normal production techniques and then removed from the production line to facilitate electrical testing which is used to infer the critical dimensions. In other techniques, normal wafers are pulled from the production line and scanned (using, for example, scanning electron microscopes) to determine critical dimensions. Although such techniques do provide useful information, they tend to be expensive and/or slow and/or reduce production yield.
By way of background, critical dimensions that are relatively large by current standards could be directly measured by inspection with a scanning electron microscope using the current of back-scattered electrons to detect the edges of the features including the critical dimension of interest. However, this technique requires a relatively long period of time to complete (e.g. 10 seconds) and precision is limited to about five nanometers.
When evaluating critical dimensions within a wafer, it is generally desirable to perform numerous measurements (e.g. a few dozen to several hundred sites per field over a matrix of several dozen fields on a wafer). This permits the detection of variations that may occur across the face of the wafer. Such numbers of measurements require substantial time, particularly when about ten seconds are required for each individual measurement with electron microscopy, as alluded to above. Further, scanning electron microscopy requires measurements to be made at high vacuum levels, which takes additional time to achieve. Such a long measurement time adversely impacts throughput, especially in a manufacturing environment. Additionally, precision of about or less than one nanometer is required for integrated circuit designs at the current state of the art. Increasing electron beam power to reduce measurement time and/or increase precision tends to erode the pattern being measured. Other problems have also been associated with scanning electron microscope measurements to test in the manufacturing environment. For example, the nature of electron microscopy requires bombardment of a substrate with particles and the resultant secondary emissions that are captured for imaging can contaminate devices in integrated circuits adjacent the test patterns when applied to manufacturing environments. In such environments, the wafer used for the test exposure is often discarded or the resist removed and the wafer reprocessed without measurements being concurrently made. Moreover, the cost of specialized electron microscope measurements coupled with the low throughput thereof add significantly to the cost of integrated circuit manufacture.
Another critical dimension measurement technique employs an electrical measurement of an array of test structures. The test structures used in this process are formed in a conductive layer overlying a special test substrate where the structures have attached contact regions. Thus, a resist layer is exposed and the pattern of test structures developed and etched. After removing the resist layer, the conductivity of the etched features are measured by an electrical means. Using such parameters as the specific electro-conductivity of the conductive layer and the length of the etched feature, a linewidth is calculated. However, as the procedure involves a special substrate this tends to be a very expensive approach to critical dimension measurement.
Although the existing techniques do provide information that is useful in inferring critical dimensions of features within an integrated circuit, there are continuing efforts to further improve the measurement of critical dimensions of etched features.